1. Field of the Invention
The present invention relates to a delay locked loop (DLL), and more particularly to, a DLL which can remove a skew of a clock and an output data in a read operation of a double data rate synchronous DRAM (DDR SDRAM).
2. Discussion of Related Art
In general, a clock is used as a reference for adjusting an operational timing in a system or circuit, and also used to perform a faster operation without errors. When an external clock is used inside the system or circuit, a time delay (clock skew) occurs by inside circuits. A DLL compensates for the time delay, so that an internal clock can have the same phase as that of the external clock.
The essential factors of the DLL include a small area, a small jitter and a fast locking time, which are performances required by a future semiconductor memory device characterized by a low voltage high speed operation. However, the conventional arts satisfy only part of the factors, or restrict the low voltage high speed operation.
On the other hand, the DLL is less influenced by noises than a phase locked loop (PLL), and thus is widely employed for a synchronous semiconductor memory device such as a DDR SDRAM. Especially, a register controlled DLL has been generally used. The disadvantages of the conventional register controlled DLL will now be explained.
FIG. 1 is a block diagram illustrating the conventional register controlled DLL.
An input buffer 101 buffers external clocks CLK and /CLK. A variable delay line 102 delays the buffered external clocks CLK and /CLK. A replica 105 is modeled to have the same delay time as an access time (tAC) path. A phase detector 103 detects a phase difference between a reference clock ref_clk from the input buffer 101 and a feedback clock fb_clk from the replica 105. A control circuit 104 determines a delay amount of the variable delay line 102 according to the output from the phase detector 103. An output buffer 106 generates an internal clock iCLK by buffering the output from the variable delay line 102.
The operational range of the DLL is determined by the delay time of the variable delay line 102 and the delay time of the replica 105. In general, the operational range of the DLL is prescribed by the spec. of the DDR SDRAM, and has the maximum period of 15 ns. Accordingly, the DLL cannot be normally operated in a test apparatus having a clock period over 30 ns in a wafer test. It is thus impossible to perform logic verification relating to the DLL or defect analysis in a wafer level. In addition, the DLL is not operated in the wafer level, and thus the tAC value is not adjusted, which results in a low yield in a package level.